1. Field of the Invention
The present invention relates to a random access memory (RAM) which has a small cycle time period compatible with static RAM's which can carry out a so-called read-modified write operation.
2. Description of the Related Art
Recently, dynamic RAM's have come into increased use for storing video data. Such devices must allow a large amount of data to be read out and written therein per unit time, i.e., must offer a reduced cycle time period. Generally, in a dynamic RAM, each cycle time period includes one access time period for an actual read/write operation and one reset time period for precharging each portion of the device prior to each access operation. The reset time period is of the same order as an access time period. Therefore, each cycle time period of a dynamic RAM is relatively long.
In the prior art, a small cycle time period is available with a static column type dynamic RAM (F. Baba et al, "A 35 ns 64K Static Column DRAM", 1983 IEEE ISSCC Digest of Technical Papers, Article WPM6.5, pp.65-64, Febuary 1983). This dynamic RAM offers a cycle time period during a page mode about the same as its access time period. This dynamic RAM, however, includes static circuits. Therefore, there is a disadvantage of a rather large power consumption.
In another prior art dynamic RAM offering a small cycle time period (U.S. Pat. No. 4,376,989), each circuit thereof is automatically reset, i.e., precharged by the subsequent circuit thereof after the completion of its own operation. Therefore, its own reset time period is small, thereby reducing the cycle time period. In such a dynamic RAM, however, since all the circuits thereof are automatically reset, it is impossible to carry out a read-modified write operation. As a result, a dynamic RAM of this type is not compatible with conventional dynamic RAM's.